It is often desired in an integrated circuit to delay a signal. In the context of a periodic signal like a clock signal, adjustment of delay can be understood as an adjustment of the phase of the signal. Such phase shifting of a clock signal is particularly useful as applied to delay lock loops (DLLs) or phase lock loops (PLLs) that are used to generate internal clock signals for an integrated circuit from a master clock signal. Because the of complexity of modern-day integrated circuits, the ability to finely shift the phase of clock signal is particularly important to ensure proper timing within the circuit.
Techniques have been previously disclosed to provide such fine phase shifts in clock signals. See, e.g., U.S. patent application Ser. No. 10/722/959 (“the '959 application”), entitled “Digital Delay-Locked Loop Circuits with Hierarchical Delay Adjustment,” filed Nov. 26, 2003, and assigned to the assignee of the present application, Micron Technology, Inc. As the present application builds on the techniques disclosed in the '959 application, the '959 application is hereby incorporated by reference in its entirety. The reader's knowledge of the '959 application is presumed, and as a result a detailed discussion of background is limited in this disclosure.
In the '959 application, a hierarchical delay line 10 is disclosed, which is illustrated in FIGS. 1A and 1B of the present application. These hierarchical delay lines 10 are used to finely adjust the phase difference of the output signal (Clk_Out) relative to the input signal (Clk_In). Both delay lines 10 are hierarchical, meaning that each has a number of different stages involved in “fine tuning” the phase shift. FIG. 1A has a dual hierarchy, while FIG. 1B has a triple hierarchy. Discussed below is the operation of the triple hierarchy delay line 10 of FIG. 1B.
The first stage in FIG. 1B comprises two variable delay lines (VDLs) 12, 14 used to provide a coarse phase shift in the input signal. The coarse phase shift is determined by VDL control signals (VDLcntr) to the VDLs 12, 14, which is shown in further detail in FIG. 1C. As shown, multiple control signals (Sel<1:4>) are used for each VDL 12, 14. Depending on which Sel<x> signal is chosen, the input signal (Clk_In) will be delayed through the various “coarse units delays” (CUDS) provided by the VDL 12, 14. In the example shown in FIG. 1C, there are four Sel<x> control signals and hence four CUD stages, which can cause the input signal to be delayed by 1, 2, 3, or 4 CUDs (i.e. from tCUD to 4tCUD). It is worth mentioning that other types of VDLs can be used besides the circuitry shown in FIG. 1C.
In the second stage of the triple hierarchical delay line of FIG. 1B, phase mixers (PM) 16, 18 are used to provide an intermediate phase between the two phases output from the VDLs 12, 14 (i.e., inA, inB). This is only briefly explained as the same is well explained in the above-incorporated '959 application. As shown in FIG. 1D, the phase mixers 16, 18 comprise two variable inverters 19, 21. The variable inverters 19, 21 are controllable using control signals S<1:N>, corresponding to phase mixer control signals (PMcntrx) from FIGS. 1A and 1B. The circuitry for the variable inverters 19, 21, shown to the right in FIG. 1D, allows, depending on the signals S<x> chosen, the output of the phase mixer to be “weighted” between one of the two input phases (inA, inB). For example, if all signals S<x> are high, the output will equal inB (i.e., k=1). If all signals S<x> are low, the output will equal inA (k=0). If only some are chosen (e.g., half), then the output will be the intermediate phase between inA and inB, as shown at the bottom of FIG. 1D (k=0.5). (“k” equals p/N, where p equals the number of S<x> signals activated (0 through N), and N equals the total number of S<x> signals). In any event, in this second stage, the phase difference between the VDLs 12, 14, is tailored so that the outputs of the phase mixers 16, 18, express an even finer phase difference.
Referring again to FIG. 1B, in the third stage, the outputs from the two phase mixers 16, 18, are sent to another similar phase mixer 20. Here again, the fine phase difference between the inputs to the third stage are once again rendered finer still at the output of third stage, Clk_Out, i.e., the output of the hierarchical delay line 10.
In this way, a very tightly controlled phase difference may be expressed between the Clk_In signal and the Clk_Out signal. For example, if we assume that the first (coarse) stage gave rise to a phase shift of tCUD, and that each of the phase mixers 16, 18, and 20 can generate N phases (i.e., there are N control signals S<N>), then the second stage can vary the phase in increments of tCUD/N, and the third stage (i.e., the entirety of the hierarchical delay line 10) can vary the phase in increments of tCUD/N^2. For example, if tCUD=90 degrees, and if each phase mixer 16, 18, 20 had three control signals (i.e., N=3), then the hierarchical delay line 10 can vary the phase difference between Clk_In and Clk_Out in 10 degree increments. Of course, and as explained in the '959 application, further fine-adjustment phase mixer stages can be added to even further reduce the phase increment between Clk_In and Clk_Out. For example, for Q phase mixer stages, and assuming N control signals in the phase mixers at each stage, the increment value would equal tCUD/N^Q. Through such fine phase shift control, phase shifts on the order of picoseconds can be achieved.
While satisfactory in operation, the hierarchical delay lines 10 of FIGS. 1A and 1B have disadvantages. For example, the VDL blocks 12, 14 in the circuit are very layout intensive and consume significant power. Although only a few CUD stages are shown in the VDL of FIG. 1C, in reality a VDL would contain tens of CUDs. This in turn necessitates many control signals Sel<x> and logic to generate them. In short, it can be argued that the approach of the hierarchical delay lines 10 of FIGS. 1A and 1B are generally too big, too complicated, and too power-intensive.